CVE-2025-63384
Nov. 10, 2025, 8:15 p.m.
None
No Score
Description
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET (Supervisor-mode Exception Return) instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode (M-mode) to Supervisor-mode (S-mode) as specified by the sstatus.SPP bit, the processor incorrectly remains in M-mode, leading to a critical privilege retention vulnerability.
Product(s) Impacted
| Vendor | Product | Versions |
|---|---|---|
| Risc-v |
|
|
Weaknesses
Common security weaknesses mapped to this vulnerability.
*CPE(s)
Affected systems and software identified for this CVE.
| Type | Vendor | Product | Version | Update | Edition | Language | Software Edition | Target Software | Target Hardware | Other Information |
|---|---|---|---|---|---|---|---|---|---|---|
| a | risc-v | rocket-chip | / | / | / | / | / | / | / | / |
Tags
Timeline
Published: Nov. 10, 2025, 8:15 p.m.
Last Modified: Nov. 10, 2025, 8:15 p.m.
Last Modified: Nov. 10, 2025, 8:15 p.m.
Status : Received
CVE has been recently published to the CVE List and has been received by the NVD.
More infoSource
cve@mitre.org
*Disclaimer: Some vulnerabilities do not have an associated CPE. To enhance the data, we use AI to infer CPEs based on CVE details. This is an automated process and might not always be accurate.