Products
Intel Processor
Source
secure@intel.com
Tags
CVE-2024-24853 details
Published : Aug. 14, 2024, 2:15 p.m.
Last Modified : Aug. 14, 2024, 5:49 p.m.
Last Modified : Aug. 14, 2024, 5:49 p.m.
Description
Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.
CVSS Score
| 1 | 2 | 3 | 4 | 5 | 6 | 7.2 | 8 | 9 | 10 |
|---|
Weakness
| Weakness | Name | Description |
|---|---|---|
| CWE-696 | Incorrect Behavior Order | The product performs multiple related behaviors, but the behaviors are performed in the wrong order in ways which may produce resultant weaknesses. |
CVSS Data
Attack Vector
LOCAL
Attack Complexity
HIGH
Privileges Required
HIGH
Scope
CHANGED
Confidentiality Impact
HIGH
Integrity Impact
HIGH
Availability Impact
HIGH
Base Score
7.2
Exploitability Score
0.6
Impact Score
6.0
Base Severity
HIGH
Vector String : CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:H
References
| URL | Source |
|---|---|
| https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01083.html | secure@intel.com |
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