CVE-2024-24853

Aug. 14, 2024, 5:49 p.m.

7.2
High

Description

Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM) in some Intel(R) Processor may allow a privileged user to potentially enable escalation of privilege via local access.

Product(s) Impacted

Product Versions
Intel Processor
  • []

Weaknesses

Common security weaknesses mapped to this vulnerability.

CWE-696
Incorrect Behavior Order
The product performs multiple related behaviors, but the behaviors are performed in the wrong order in ways which may produce resultant weaknesses.

References

https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01083.html

Tags

secure@intel.com
CWE-696
2024-08-14
CVE-2024-24853

CVSS Score

7.2 / 10

CVSS Data - 3.1

  • Attack Vector: LOCAL
  • Attack Complexity: HIGH
  • Privileges Required: HIGH
  • Scope: CHANGED
  • Confidentiality Impact: HIGH
  • Integrity Impact: HIGH
  • Availability Impact: HIGH

    • CVSS:3.1/AV:L/AC:H/PR:H/UI:R/S:C/C:H/I:H/A:H

    View Vector String

Timeline

Published: Aug. 14, 2024, 2:15 p.m.
Last Modified: Aug. 14, 2024, 5:49 p.m.

Status : Awaiting Analysis

CVE has been recently published to the CVE List and has been received by the NVD.

More info

Source

secure@intel.com

*Disclaimer: Some vulnerabilities do not have an associated CPE. To enhance the data, we use AI to infer CPEs based on CVE details. This is an automated process and might not always be accurate.