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CVE-2026-23554

· Published 23/03/2026 07:16 · Modified 23/03/2026 15:16

Labels: CVE-2026-23554 2026-03-23CVE-2026-23554CWE-367[email protected]

Essential information

Published
23/03/2026 07:16
Modified
23/03/2026 15:16
Author
Creator
CVSS
7.8 HIGH (v3.1)
CISA KEV
No
CWE
CVSS vector
CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:H/A:H

CVSS metrics

Description

The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush. Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.

NVD status

Status
Awaiting Analysis — CVE has been recently published to the CVE List and has been received by the NVD.
Source
[email protected]
NVD
View on NVD

Affected products (CPE)

ProductCPE
intel / ept cpe:2.3:a:intel:ept:*:*:*:*:*:*:*:*
xen / xen cpe:2.3:a:xen:xen:*:*:*:*:*:*:*:*

References